The present invention relates generally to an apparatus and method for testing logic on circuit chips. In particular, the present invention relates to structure and function of the test logic within the main logic of a chip for partial-scan built-in self-test on a circuit chip.
The number of devices, also called transistors, on a commonly available integrated circuit may be very large. Very Large Scale Integrated (xe2x80x9cVLSIxe2x80x9d) circuits with 15 million devices have been developed. The present trend in integrated circuit design is toward even higher levels of circuit integration, thereby reducing costs and improving circuit reliability. As IC technologies continue to develop, it is expected that circuits with at least 100,000,000 devices will become common.
Increased circuit integration is not, however, obtained without drawbacks. Increasing chip testing costs tend to reduce the benefits derived from more economically efficient design and production techniques. Typically, the costs associated with integrated circuit chip testing increases more than the increase in the number of devices thereon. Large expenses are incurred in the development of computer programs for running test routines. The engineering effort and computer time needed to devise these test routines may even exceed the requirements for designing the chip itself. It is not uncommon to employ as many engineers to develop tests for an IC to assure the quality of the part as the number of engineers designing a part.
Depending upon the particular type of circuit involved, circuit chip testing costs can now account for roughly 10 to 40 percent of the total manufacturing costs. The most commonly used technique of IC testing is known as scan design. Scan design requires the circuit designer to break complex logic circuits into smaller blocks, and to include artificial pathways into and between the blocks for data transmission. Complex sequential circuitry is thereby temporarily converted to combinational circuitry for testing purposes.
Scan design techniques are far from optimal. Scan design does not, in general, permit faults to be isolated to a particular chip or wire net. The inclusion of additional test points and transmission paths required for scan design degrades overall IC performance. Scan design also requires additional clock circuitry and relatively complicated maintenance software.
Another testing technique, one that is becoming increasingly popular, is the built-in self-test technique. As its name implies, built-in self-test, or BIST, test systems are fabricated on the IC chip to be tested. BIST systems include a pattern or operand generator for producing test operands. Each test operand is applied to the IC logic, and the response thereto analyzed by means of a shift register. The response to thousands, and even millions, of test operands is then compressed into a xe2x80x9csignaturexe2x80x9d, which is compared to predetermined signatures for a go/no go indication of the IC""s operation. One such BIST system is disclosed in the Van Brunt U.S. Pat. No. 4,357,703.
The BIST approach to circuit testing offers numerous advantages. BIST has minimal impact upon main logic functions since it is typically fabricated on the sparsely used peripheral areas of the integrated circuit chip. Since test results are processed by the BIST system, the number of tasks which must be performed by external test equipment is reduced. Specially developed maintenance software is therefore greatly reduced. Dynamic testing at full system clock rates significantly reduces system test times. BIST systems can also be used for testing integrated circuits at the wafer, chip, and system levels. Since they are independent of specific chip logic functions, BIST test systems can be used on any number of different types of circuit chips. The BIST approach also permits IC chips to be tested after they have been assembled into a computer, even though they are inaccessible to more traditional maintenance techniques. This will be the case, for example, when the IC is immersed in a liquid coolant to increase its performance.
Even though BIST test systems offer many advantages over alternative techniques, BIST test systems have yet to be developed to their fall potential. BIST testing systems have significant shortcomings when used in integrated circuits having 100,000 or more devices. BIST systems usually generate random numbers as test operands. The quality of many of the test operands, in terms of stressing the part, may be poor. When an integrated circuit has a high number of devices or transistors and as the operand goes deeper and deeper into the logic on the integrated circuit, the test becomes less and less effective. If there is a defect in the integrated circuit at a latch in the middle of the integrated circuit, there is a distinct possibility that the defect may go undetected. Certain areas of the integrated circuit may be untestable in that a defect may not propagate through many layers of logic and to an output pin to cause a test result indicating a defect. The result is that the integrated circuit may test xe2x80x9cgoodxe2x80x9d when it is really a defective part that should be scrapped.
As a result, there is need for a method and apparatus for determining if a logic module may have a portion that is untestable. Furthermore, there is a need for a flexible self-testing method and apparatus that is adaptable and can be used to sensitize certain paths on an integrated circuit so that the fault that might otherwise go unnoticed is output to the output pins. There is also a need for developing a testing method and apparatus that can be used by the logic designer or logician to add logic during the design phase to sensitize paths to untestable areas. There is also a need for developing a testing method and apparatus that can be used by the logic designer or logician to add logic during the design phase to make a logic block more testable. There is also a need for a flexible method and apparatus which can be used to control the test as well as the type of test that to be executed. Furthermore, there is a need for a method and apparatus that tests the integrated circuit to the extent necessary to determine if the part is good or bad. Furthermore, it would be advantageous if the testing method also could interface with a boundary scan type test, such as JTAG. JTAG is a boundary scan standard, found at IEEE/ANSI 1149.1-1990, which is a collection of design rules applied principally at the integrated circuit level. It would also be advantageous if the power to the logic used for testing the integrated circuit could be powered down when the integrated circuit is not under test to save power and reduce the overall cooling load on the computer. This would lower the amount of energy used and reduce the costs associated with operating the computer.
A digital integrated circuit apparatus includes main logic for performing logic operations. The main logic is further comprised of a plurality of logic modules, each having at least one logic block associated with the logic module. Many times several logic blocks are associated with the logic modules. A logic module is an internal logic block of an IC under test. The main logic further also includes a number of input pins for receiving data and a number of output pins for outputting data from the main logic. Also included on the integrated circuit apparatus is testing logic for performing dynamic tests of the main logic. The testing logic further includes a first type of built-in testing logic for testing a first number of the logic modules of the main logic and a second type of built-in test logic for testing a second number of logic blocks. The first type of built-in testing logic could be logic known as BIST. The second number of logic blocks connected to the second type of built-in scan logic are generally untestable using the first type of built-in logic. The second type of testing logic includes a test data input for inputting test data to the second type of testing logic and to the input pins of the main logic, and a test data output for outputting test data from the second type of testing logic and from the main logic. The second type of built-in scan logic includes an internal scan ring.
The testing logic also includes a command register for receiving commands and outputting control signals to control the main logic and the testing logic. The control signals output from the command register included generation of data, and shifting of data. One of the commands is for substantially powering down the testing logic on the logic chip when the logic chip is not under test.
Advantageously, the invention includes a method and apparatus for determining if a logic module may have a portion that is untestable and a method and apparatus for testing the untestable portions. The invention also provides a method and apparatus that can be used by the logic designer or logician to add logic during the design phase to sensitize paths to untestable areas. The invention provides a flexible self-testing method and apparatus that is adaptable and can be used to sensitize certain paths on an integrated circuit so that faults that might otherwise go unnoticed are output to the output pins. The command register of the invention also provides for flexible control of the test as well as flexibility in the types of test to be executed. An additional advantage of the testing method is that it can also could do boundary scan type testing, much like the JTAG standard, found at IEEE/ANSI 1149.1-1990. The command register can also power down the logic used for testing the integrated circuit when the integrated circuit is not under test. This saves power and reduces the overall cooling load on the computer.